Hand-authored MIL.
Generate MILSpec programs from native Swift, assemble ML packages and compile with Apple's public Core ML toolchain. No entitlement bypass or private kernel access.
THE BUILD PATH ↗MACBRAINS LABS / APPLE NEURAL ENGINE / 2026
Compute
placement.
Not folklore.
We reconstruct how neural networks reach the Apple Neural Engine: tensor contracts, hand-authored Core ML graphs, compiler lowering, execution placement, and measured behavior on silicon.
APPLE SILICON / A18 PROCORE ML / MILSWIFT / NATIVE
FIELD RECORD / QWEN-28L-LUT4MEASURED
PRODUCTION INFER GRAPH
2,090 / 79
ANE-assigned / CPU-assigned operations
ANE 96.4%CPU 3.6%
QUANTIZATIONLUT4
DECODER DEPTH28 L
STATE OPERATIONSANE
CPU RESIDUALARGMAX
SOURCE: ANE-RE / D210, D263 · MLComputePlan classification; not a hardware trace.
01 / THROUGHPUT102.1 tok/sQwen2.5 1.5B · batch=4 · aggregate · on-device
02 / PLACEMENT743 / 743LFM S2 production artifact · compute ops assigned to ANE
03 / MODEL QUALITY16.8033WikiText-2 perplexity · 28-layer LUT4 Qwen artifact
01 / THE PRACTICEWork at the
Work at the
graph boundary.
“Runs on ANE” is not a binary claim. Different functions, shapes and output tails may be assigned to different devices. We separate compiler placement from numeric correctness and measured throughput.
Account for every op.
Inspect MLComputePlan assignments for state access, slices, projections, norms and output tails. A declared ANE preference is not proof of ANE residency.
READ THE ANE AUDIT ↗Parity, or it fails.
Compare sealed tensor fixtures with CPU and ANE outputs: cosine similarity, relative L2, max absolute error, and finite-value gates at each exposed boundary.
PARITY CASE STUDY ↗Falsify the ceiling.
Measure actual batch and sequence shapes. A token/s figure is discarded if its underlying model was shape-locked to one token per call.
DECODE REGIMES ↗02 / MEASUREMENT PIPELINEFrom a tensor
From a tensor
to a traceable claim.
Each result has an artifact, a device, an observation method and a bounded conclusion. We keep compilation, placement, execution and output quality as separate gates.
S00 / AUTHORSwiftMILMILSpec protobuf
S01 / PACKAGE.mlpackagetyped graph + weights
S02 / LOWERcoremlcompilerApple public path
S03 / INSPECTMLComputePlanper-op assignment
S04 / EXECUTENative runnerreal device + shape
S05 / RECONCILEParity / tok·s⁻¹falsifiable receipt
INTERPRETATION MATTERS
A model with attention and KV machinery assigned to ANE may still execute a CPU argmax tail. We report both numbers, instead of rounding the entire inference path up to “100% ANE.”
03 / FIELD NOTESSelected technical
Selected technical
records.
Short, source-bound examinations of what passed, what diverged and what earlier hypotheses failed.
N/001
N/002
N/003
28 layers, LUT4, and the cost of exact placement
State reads, indexed slices, weight.bin offsets and the non-ANE tail.
A passing production graph and a failing diagnostic one
LFM block-pair parity, 743/743 assignment and why probes alter the experiment.
The bandwidth limit that was not a limit
Batch sweeps, dispatch floors and a hypothesis overturned by measurement.
04 / RESEARCH SCOPEIndependent.
Independent.
Instrumented.
Reproducible.
MacBrains Labs is an independent engineering research identity for Apple Silicon and on-device inference. The work emphasizes native runtimes, quantized transformer execution, compiler behavior, and authorized analysis of software and infrastructure under our control.
We do not claim Apple affiliation, privileged ANE access, or universal placement results. Individual measurements refer to the named artifact, backend, tensor shape and hardware configuration. Private source artifacts are not implicitly public merely because a summary appears here.
Technical correspondence ↗